Revised Time Table for PRE-PH.D-MS EXAMS PRE-M.PHIL PRE, JAN-2010

To
The Principals of JNTUH affiliated colleges.

Sir,
Sub: JNTU Hyderabad - Resume of class work of JNTUH affiliated colleges - Rescheduling of university Examinations – Reg.


All the principals of affiliated colleges of JNTUH are hereby informed that the class work resumes from 06-01-2010. The university examinations are scheduled from 18-01-2010. The detailed schedules of all the university examinations of various courses will be announced shortly.

The principals are requested to take necessary action in this regard.

click here to download the timetable

ALL JNTU EXAMS ARE POSTPONED

All the Affilated colleges of JNTU-HYD University will remain closed from 4th To 18Th Dec.All the exams scheduled from 4th Dec are postponed.New Time Tables will be announced later...........

CLICK HERE FOR OFFICIAL LETTER

30 dec exam postponed

All the university semester end examinations (B.Tech/MBA/MCA) scheduled on 30-11-2009 are postponed(officially De cleared BY JNTU-HYD) & The Exams for B.Tech./B.Pharm 4-1 sem (R05, RR & NR) scheduled on 12th Dec will be conducted as usual ( same Timings )

Download here for official letter

RE REVISED TIME TABLE FOR JNTUH

jntu has changed time table again in view of cat examination ..............

SO GUYS CHECK IT OUT

REVISED TIME TABLE

LOGIC GATES

A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. The logic normally performed is Boolean logic and is most commonly found in digital circuits. Logic gates are primarily implemented electronically using diodes or transistors, but can also be constructed using electromagnetic relays, fluidics, optics, molecules, or even mechanical elements.

In electronic logic, a logic level is represented by a voltage or current, (which depends on the type of electronic logic in use). Each logic gate requires power so that it can source and sink currents to achieve the correct output voltage. In logic circuit diagrams the power is not shown, but in a full electronic schematic, power connections are required.

SYMBOLS AND TRUTH TABLE

Type	Distinctive shape	Rectangular shape	Boolean algebra between A & B	Truth table
AND				INPUT OUTPUT A B A AND B 0 0 0 0 1 0 1 0 0 1 1 1
OR			A + B	INPUT OUTPUT A B A OR B 0 0 0 0 1 1 1 0 1 1 1 1
NOT				INPUT OUTPUT A NOT A 0 1 1 0
In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a bubble, and is generally used in circuit diagrams to indicate an inverted (active-low) input or output.[1]
NAND				INPUT OUTPUT A B A NAND B 0 0 1 0 1 1 1 0 1 1 1 0
NOR				INPUT OUTPUT A B A NOR B 0 0 1 0 1 0 1 0 0 1 1 0
XOR				INPUT OUTPUT A B A XOR B 0 0 0 0 1 1 1 0 1 1 1 0
XNOR				INPUT OUTPUT A B A XNOR B 0 0 1 0 1 0 1 0 0 1 1 1

REVISED JNTU TIMETABLE

Hi guys due to GHMC elections in hyderabad exam dated on 23-11-2009 is postponed to 2 dec and 3 dec


check this for official notification of jntu

CLICK HERE


REVISED TIME-TABLE FOR B.TECH


External Exams Time Tabes For B.Tech 1,2,3,4 Years I & II Semesters Regular/Supply(In Pdf Format)


I YEAR TIME TABLE SUPPLY

I YEAR NR

I YEAR R05

I YEAR R07

I YEAR RR



2-2 SUPPLY TIME TABLE


II YEAR II SEM. NR

II YEAR II SEM. R05

II YEAR II SEM. RR

II YEAR II SEM. R07



3-2 SUPPLY TIME TABLE


III YEAR II SEM. NR

III YEAR II SEM. RR

III YEAR II SEM.R05



II-III-IV YEAR I SEM REGULAR/SUPPLY TIME TABLE


2-1 REGULAR/SUPPLY Time Tables


II YEAR I SEM. NR

II YEAR I SEM. R07

II YEAR I SEM. RR

II year I sem R05


3-1 REGULAR/SUPPLY Time Tables


III YEAR I SEM. NR

III YEAR I SEM.R05

III YEAR I SEM.R07

III YEAR I SEM.RR


4-1 REGULAR/SUPPLY Time Tables


IV YEAR I SEM. RR

IV YEAR I SEM.NR

IV YEAR I SEM.R05

EEE 2-1 QUESTION PAPERS

Hi guys i am giving the links for previous years question papers

download here

EEE department

FMHM
PDC
STLD
EMF
EM-1
M-3

NOV-08 PAPERS
REQUEST FOR ANY BRANCH OR YEAR....I WILL GET IT FOR U